3D package applications such as package-on-package (PoP) are becoming increasingly popular and widely used in mobile devices because they can enhance electrical performance by integrating logic chips (e.g., application processors (APs)), high capacity/bandwidth memory chips (e.g., wide input/out (WIO) chips, low power double data rate X (LPDDRx) chips, and the like), and/or other heterogeneous chips (e.g., sensors, micro-electro-mechanicals (MEMs), networking devices, and the like), for instance. However, existing PoP devices and packaging structures are challenged to meet fine channels and high density routing requirements of next-generation applications. For example, the wire bonding of a typical LPDDRx, TSVs in AP/WIO chips, and the like impose various disadvantages on the package, such as increased manufacturing cost, large package thickness, and silicon access penalties. Improved devices and methods of manufacturing the same are required.